As the level of integration in MOS transistors increases, the associated design rule can be reduced to provide smaller source/drain regions. Especially, in MOS transistors (e.g., MOSFET) with a lightly doped region, a contact region may become smaller due to spacers formed on side walls of a gate electrode of the MOSFET.
Contacts have been used in various types of devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), and central processing units (CPUs), connecting impurity regions (source/drain regions) to interconnection structures in the MOSFET (such as a bit line).
FIGS. 1 to 7 are cross-sectional views illustrating conventional methods for fabricating semiconductor devices including MOS transistors with contacts.
Referring to FIG. 1, a field region 105 is formed in a substrate 100 to define an active region. That is, the substrate 100 is etched to form a trench, and the trench is filled with a sufficient insulating material. The resultant structure is polished using chemical mechanical polishing (CMP) to form the field region 105.
Next, an insulation layer and a gate conductive layer are sequentially stacked on the substrate where the field region 105 is formed and then patterned to form a gate electrode 115. A gate insulation layer 110 is located between the substrate 100 and the gate electrode 115. Impurity ions are implanted at a low concentration using the gate electrode 115 and the field region 105 as an ion implantation mask, thereby forming lightly doped source/drain regions 120.
Referring to FIG. 2, a spacer insulation (or insulating) layer is formed on an entire surface of the substrate including the gate electrode 115 and is etched to form spacers 125 on side walls of the gate electrode 115. Thereafter, by using the gate electrode 115, the spacer 125, and the field region 105 as an ion implantation mask, impurity ions are implanted at a high concentration to form heavily doped source/drain regions 130. The lightly and heavily doped source/drain regions 120 and 130 correspond to source and drain regions of a MOS transistor. The transistor having the foregoing structure is sometime referred to as an “LDD structure” and is widely used. As is well known, in MOS transistors with an LDD structure, a lightly doped region is self-aligned to a gate electrode and is located between a channel region and a heavily doped region. A lightly doped region can decrease an electric field between the drain and the channel region. Thus, if a high voltage is applied, carriers emitted from the source may not accelerate rapidly thereby possibly reducing or avoiding “hot carrier” effects.
Referring to FIG. 3, a silicide layer 135a and 135b is formed on a top of the active region and on the gate electrode 115. A cobalt layer is deposited using sputtering and a thermal process is then applied to the resultant structure. The thermal process may allow the cobalt layer to react with the active region and the gate electrode 125, thereby creating cobalt silicide. In contrast, a silicide reaction may not occur on the field region 105 and on the spacer 125. A cleaning process using a mixed solution of sulfuric acid (H2SO4) and oxygenated water (H2O2) is applied to the semiconductor substrate when the thermal process is completed. Thus, the unsilicided metal material can be removed. The silicide layer 135a and 135b can decrease the resistance and capacitance associated with the contacts subsequently formed, thereby accelerating the speed of the devices.
Referring to FIG. 4, an etch stop layer 140 is formed on an entire surface of the substrate and on the silicide layer 135a and 135b. An interlayer dielectric (ILD) 145 is then formed on the substrate including the etch stop layer 140.
Referring to FIG. 5, the ILD 145 and the etch stop layer 140 are selectively etched to form a contact hole 150 exposing the active region between the gate electrode 115 and the field region 105. Although not shown in the drawings, the contact hole 150 can be filled with a barrier metal layer and a conductive material.
The contact hole 150 can be formed misaligned to the silicide layer 135a, which may give rise to problems such as those illustrated in FIGS. 6 and 7.
FIG. 6 shows the contact hole 150 misaligned to the silicide layer 135a as denoted by reference designator A in a borderless contact. The borderless contact can be created by exposing a portion of the field region 105 and a surface of the semiconductor substrate adjacent thereto. As shown in FIG. 6, the misalignment may cause a recess in the exposed field region 105. If a depth of the recess is more than that of a source/drain junction, or if the recess is close to a junction boundary line, the contact may be formed to be in electrical contact with the substrate, which may result in increased leakage current. It is known that as a junction becomes shallower, the borderless contact can generate increased leakage current.
FIG. 7 shows the contact hole 150 misaligned to the silicide layer 135a as denoted by reference designator B such that the contact hole 150 is formed over the spacer. In this case, an open region of the contact hole 150 may be reduced, or may even be nearly closed. As an open area of the contact hole decreases, the contact resistance increases. Furthermore, the barrier metal layer and metal may not be fully deposited to a bottom of the contact hole, thereby deteriorating the reliability of the devices.
The extended active region, the contact hole being formed, with narrow spacer on the side walls of the gate electrode can solve the foregoing problems. However, if a width of the spacer 124 is reduced, it may not be possible to form the transistor with the LDD structure having the characteristics deemed desirable.